The present invention relates to voltage multiplier circuits, and more particularly to voltage pump circuits employed in integrated circuits such as electrically erasable programmable read only memories (EEPROMs).
EEPROM devices typically employ floating gate transistors, programmed either to the depletion or enhancement mode, as the memory elements. To program the elements, a high programming voltage, typically about 17 volts, is required to induce electron tunneling to or from the floating gate. If the device is to be operated from a +5 volt supply, a circuit is required to generate an additional 12 volts. This supply circuit should also be capable of charging the large memory circuit capacitance in less than the element programming time (typically 1 millisecond).
It is known in CMOS technology to use inverting circuits comprising N channel transistors and capacitors, wherein the capacitors are charged in parallel and then connected in series to achieve voltage multiplication. The N channel transistors require P wells, which leads to several disadvantages, i.e., more chip area for an equivalent stage, less efficiency due to parasitic capacitance and an undesirable parasitic bipolar NPN device. The P wells typically require more separation between stages and therefore require a larger chip area to maintain an equivalent output current. The P wells introduce a parasitic capacitance which may be charged and discharged each cycle, thereby reducing efficiency. The possibility of latch-up is introduced by the addition of a bipolar NPN device. This is a serious disadvantage to newer processes which are more sensitive to latch-up.
Charging all the capacitors in parallel and then connecting them in series has the disadvantage that both nodes of the pumping capacitors are included in the output. Since the lower plate of the capacitor also has a parasitic capacitor coupled to its substrate, the charge is split between these two capacitors. The charge lost to the parasitic capacitor subtracts directly from the output current of the circuit. This leads to a lower output current per unit area and to a lower open circuit output voltage and lower output current per unit area. The charge splitting losses are process dependent, which leads to lot-to-lot variations in output voltage and current.
It would therfore be an advance in the art to provide a voltage multiplier circuit with a very high efficiency which is less process dependent. It would further by advantageous to provide a voltage multiplier with increased layout density and current drive capability, and in which the possibility of latch-up has been eliminated.